1. Field of the Invention
The present invention relates to a semiconductor memory device having plural memory cell array portions and a column decoder portion between these memory cell array portions. The semiconductor memory device according to the present invention is used, for example, as a dynamic random access memory (DRAM).
2. Description of the Related Art
Recently, an arrangement of the semiconductor memory device such as a DRAM has been used in which a decoder portion is located at the central part of the semiconductor memory device between a plurality of memory cell array portions. Such an arrangement is desirable to reduce differences in the transmission time from the decoder to a memory cell relatively close to the decoder and to a memory cell relatively far from the decoder.
In the above-described arrangement, since the distance between the adjacent bit lines has been reduced because of the reduction of pitch of a memory cell due to the highly integrated, highly concentrated structure of a semiconductor memory device, the width of a driver circuit in a column decoder along the direction perpendicular to the bit lines is required to be reduced. Such reduction of the width of the driver circuit causes an increase in the width of the driver circuit along the direction of the bit lines, and hence a considerable increase in the area of the column decoder.
This situation causes difficulty in further increasing the capacity of a semiconductor memory device.